The present invention relates generally to the fabrication of integrated circuits. More particularly, the present invention relates to a process for fabricating contacts for integrated circuit devices.
Contacts are required in an integrated circuit device to provide electrical connections between layers or levels of the integrated circuit device. Semiconductor devices typically include a multitude of transistors which are coupled together in particular configurations through the use of contacts.
In a conventional flash memory cell, a memory cell includes a stacked gate, a drain, and a source. A drain contact electrically connects the drain of the memory cell to a conductive layer (a bit line) above the stacked gate. The conductive layer can be a polysilicon layer, first metal layer, or other layer utilized to connect a bit line to a storage node (drain) of the memory cell.
Additionally, the source of the memory cell is often coupled to a source line with a VSS implant (e.g., a VSS connector or a self-aligned source (SAS) module). Sources of neighboring transistors are coupled together at the substrate level (in the active region). The SAS module is typically fabricated according to the following steps: a SAS mask and etch of LOCOS oxide, a VSS connection mask and implant. Module fabrication requires two critical masking steps, one during the SAS mask and etch and another during the VSS connection mask and implant.
The fabrication steps related to the SAS module can be somewhat disadvantageous. Etching steps can cause charge damage in the active region. Also, the SAS module can be disadvantageous due to its sheet resistance and size.
Contacts associated with the flash memory cell must be spaced from the polysilicon associated with the stacked gate. As feature sizes are reduced according to integrated circuit processes, smaller dimensions are required to achieve higher packing densities. Generally, contacts must be spaced apart from the stacked gate so alignment errors do not result in a shorting of the stacked gate with the source contact or the drain contact. The spacing between the contact and gate contributes to the overall size of the flash memory cell.
Thus, there is a need to eliminate the need for a SAS module. Further, there is a need to relax contact to gate spacing requirements. Further still, there is a need for a flash memory with a smaller cell size. Further still, there is a need to reduce VSS source line resistance.